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MYSON TECHNOLOGY
FEATURES
* Horizontal sync input may be up to 130 KHz. * Acceptable wide-range pixel clock up to 96MHz. * Full screen display consists of 15 (rows) by 30 (columns) characters. * 12 x 18 dot matrix per character. * Total 272 characters and graphic fonts including 256 standard and 16 multi-color mask ROM fonts. * 8 color selectable maximum per display character. * 7 color selectable maximum for character background. * Double character height and/or width control. * Programmable positioning for display screen center. * Bordering, shadowing and blinking effect. * Programmable character height (18 to 71 lines) control. * Row to row spacing register to manipulate the constant display height. * 4 programmable background windows with multi-level operation and shadowing on window effect. * Software clears bit for full-screen erasing. * Half tone and fast blanking output. * Fade-in/fade-out effect. * 8 channels 8 bits PWM D/A converters output. * Compatible to SPI bus or I2C interface with slave address 7AH (Slave address is mask option). * 16 / 20 / 24 pins PDIP / SOP package.
MTV121
Super On-Screen-Display for LCD Monitor
GENERAL DESCRIPTION
MTV121 is designed for LCD monitor applications to display the built-in characters or fonts onto an LCD monitor screen. The display operation is by transferring data and control information from micro controller to RAM through a serial data interface. It can execute full screen display automatically and specific functions such as character background color, bordering, shadowing, blinking, double height and width, font by font color control, frame positioning, frame size control by character height and row-torow spacing, horizontal display resolution, full-screen erasing, fade-in/fade-out effect, windowing effect and shadowing on window. MTV121 provide 256 standard and 16 multi-color fonts for more efficacious applications. The full OSD menu is formed of 15 rows x 30 columns which can be positioned on anywhere of the monitor screen by changing vertical delay or horizontal delay. Moreover, MTV121 also provide 8 PWM DAC channels with 8 bits resolution and a PWM clock output for external digital to analog control.
BLOCK DIAGRAM
SSB 8DATA SCK DATA 8 VDD LUMAR LUMAG LUMAB BLINK 8 CRADDR
SERIAL DATA INTERFACE
9ROW, COL ACK CWS CHS
DISPLAY & ROW CONTROL REGISTERS
VSS
SDA DATA ARWDB HDREN VDREN NROW 8 5 5 9 9 5 5 RCADDR DADDR FONTADDR WINADDR PWMADDR
VDDA
ADDRESS BUS ADMINISTRATOR
LPN CWS VCLKS
CHARACTER ROM USER FONT RAM LUMINANCE & BORDGER GENERATOR
LUMA VSSA BORDER
VFLB VSP CH 7 CHS VERTD 8
VERTICAL DISPLAY CONTROL
HORIZONTAL DISPLAY CONTROL CLOCK GENERATOR
5 LPN NROW VDREN
DATA 8 8 VERTD 8 HORD 7 CH
WINDOWS & FRAME CONTROL
WR WG WB FBKGC BLANK
BSEN SHADOW OSDENB HSP VSP
HFLB HSP NC XIN PWM0 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 HORD 8
ARWDB HDREN LUMAR LUMAG LUMAB BLINK VCLKX
ROUT GOUT BOUT FBKG HTONE
VCLKX
COLOR ENCODER
PWM D/A CONVERTER
8 DATA
POWER ON RESET
PRB
This datasheet contains new product information. Myson Technology reserves the rights to modify the product specification without notice. No liability is assumed as a result of the use of this procuts. No rights under any patent accompany the sales of the product. 1/18 MTV121 Revision 5.0 06/29/1999
MYSON TECHNOLOGY
1.0 PIN CONNECTION
VSSA XIN NC VDDA HFLB SSB SDA SCK
1 2 3 4 5 6 7 8 16 15 14 13
MTV121
VSS ROUT GOUT BOUT FBKG HTONE/PWMCK VFLB VDD
VSSA XIN NC VDDA HFLB SSB SDA SCK PWM0 PWM1
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16
VSS ROUT GOUT BOUT FBKG HTONE/PWMCK VFLB VDD PWM7 PWM6
VSSA XIN NC VDDA HFLB SSB SDA SCK PWM0 PWM1 PWM2 PWM3
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19
VSS ROUT GOUT BOUT FBKG HTONE/PWMCK VFLB VDD PWM7 PWM6 PWM5 PWM4
MTV121
12 11 10 9
MTV121N20
15 14 13 12 11
MTV121N24
18 17 16 15 14 13
2.0 PIN DESCRIPTIONS
Pin No. Name VSS XIN I/O I N16 N20 N24 1 2 1 2 1 2 Descriptions Ground. This ground pin is used to internal circuitry. Pixel clock input. This is a clock input pin. MTV121 is driven by an external pixel clock source for all the logics inside. The frequency of XIN must be the integral time of pin HFLB. No connection. Power supply. Positive 5 V DC supply for internal circuitry. And a 0.1uF decoupling capacitor should be connected across to VDD and VSS. Horizontal input. This pin is used to input the horizontal synchronizing signal. It is a leading edge triggered and has an internal pull-up resistor. Serial interface enable. It is used to enable the serial data and is also used to select the operation of I2C or SPI bus. If this pin is left floating, I2C bus is enabled, otherwise the SPI bus is enabled. Serial data input. The external data transfer through this pin to internal display registers and control registers. It has an internal pull-up resistor. Serial clock input. The clock-input pin is used to synchronize the data transfer. It has an internal pull-up resistor. Open-Drain PWM D/A converter 0. The output pulse width is programmable by the register of Row 15, Column 23. Open-Drain PWM D/A converter 1. The output pulse width is programmable by the register of Row 15, Column 24. Open-Drain PWM D/A converter 2. The output pulse width is programmable by the register of Row 15, Column 25. Open-Drain PWM D/A converter 3. The output pulse width is programmable by the register of Row 15, Column 26.
NC VDD HFLB SSB
I I I
3 4 5 6
3 4 5 6
3 4 5 6
SDA SCK PWM0 PWM1 PWM2 PWM3
I I O O O O
7 8 -
7 8 9 10 -
7 8 9 10 11 12
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Name PWM4 PWM5 PWM6 PWM7 VDD VFLB HTONE / PWMCK FBKG BOUT GOUT ROUT VSS I/O O O O O I O 9 10 11 Pin No. N16 N20 N24 11 12 13 14 15 13 14 15 16 17 18 19 Descriptions
MTV121
Open-Drain PWM D/A converter 4. The output pulse width is programmable by the register of Row 15, Column 27. Open-Drain PWM D/A converter 5. The output pulse width is programmable by the register of Row 15, Column 28. Open-Drain PWM D/A converter 6. The output pulse width is programmable by the register of Row 15, Column 29. Open-Drain PWM D/A converter 7. The output pulse width is programmable by the register of Row 15, Column 30. Power supply. Positive 5 V DC supply for internal circuitry and a 0.1uF decoupling capacitor should be connected across to VDD and VSS. Vertical input. This pin is used to input the vertical synchronizing signal. It is leading triggered and has an internal pull-up resistor. Half tone output / PWM clock output. This is a multiplexed pin selected by PWMCK bit. This pin can be a PWM clock or used to attenuate R, G, B gain of VGA for the transparent windowing effect. Fast Blanking output. It is used to cut off external R, G, B signals of VGA while this chip is displaying characters or windows. Blue color output. It is a blue color video signal output. Green color output. It is a green color video signal output. Red color output. It is a red color video signal output. Ground. This ground pin is used to internal circuitry.
O O O O -
12 13 14 15 16
16 17 18 19 20
20 21 22 23 24
3.0 FUNCTIONAL DESCRIPTIONS
3.1 SERIAL DATA INTERFACE
The serial data interface receives data transmitted from an external controller. And there are 2 types of bus can be accessed through the serial data interface, one is SPI bus and other is I2C bus. 3.1.1 SPI bus While SSB pin is pulled to "high" or "low" level, the SPI bus operation is selected. And a valid transmission should be starting from pulling SSB to "low" level, enabling MTV121 to receiving mode, and retain "low" level until the last cycle for a complete data packet transfer. The protocol is shown in Figure 1.
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SSB
MTV121
SCK
SDA
MS B
first byte last byte
LSB
FIGURE 1. Data Transmission Protocol (SPI) There are three transmission formats shown as below: Format (a) R - C - D R - C - D R - C - D Format (b) R - C - D C - D C - D C - D Format (c) R - C - D D D D D D Where R=Row address, C=Column address, D=Display data 3.1.2 I2C bus I2C bus operation is only selected when SSB pin is left floating. And a valid transmission should be starting from writing the slave address 7AH, which is mask option, to MTV121. The protocol is shown in Figure 2.
SCK
SDA
START
B7
B6
first byte
B0
ACK
B7
B0
ACK STOP
@@@@ @ second byte last byte
FIGURE 2. Data Transmission Protocol (I2C) There are three transmission formats shown as below: Format (a) S - R - C - D R - C - D R - C - D Format (b) S - R - C - D C - D C - D C - D Format (c) S - R - C - D D D D D D Where S=Slave address, R=Row address, C=Column address, D=Display data Each arbitrary length of data packet consists of 3 portions viz, Row address (R), Column address (C), and Display data (D). Format (a) is suitable for updating small amount of data which will be allocated with different row address and column address. Format (b) is recommended for updating data that has same row address but different column address. Massive data updating or full screen data change should use format (c) to increase transmission efficiency. The row and column address will be incremented automatically when the format (c) is applied. Furthermore, the undefined locations in display or fonts RAM should be filled with dummy data. There are 2 types of data should be accessed through the serial data interface, one is ADDRESS bytes of display registers, and other is ATTRIBUTE bytes of display registers, the protocol are same for all except bit5 of row address. The MSB(b7) is used to distinguish row and column addresses when transferring data from external controller. The bit6 of column address is used to differentiate the column address for format (a), (b) and format (c) respectively. Bit5 of row address for display register is used to distinguish ADDRESS byte when it is set to "0" and ATTRIBUTE byte when it is set to "1". See Table 1 on page 4.
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TABLE 1. The configuration of transmission formats. Address Row Address Bytes of Display Reg. Column ab Columnc Row Attribute Bytes of Display Reg. Column ab Columnc b7 1 0 0 1 0 0 b6 0 0 1 0 0 1 b5 0 x x 1 x x b4 x C4 C4 x C4 C4 b3 R3 C3 C3 R3 C3 C3 b2 R2 C2 C2 R2 C2 C2 b1 R1 C1 C1 R1 C1 C1 b0 R0 C0 C0 R0 C0 C0
MTV121
Format a,b,c a,b c a,b,c a,b c
The data transmission is permitted to change from format (a) to format (b) and (c), or from format (b) to format (a), but not from format (c) back to format (a) and (b). The alternation between transmission formats is configured as the state diagram shown in Figure 3.
0, X
Initiate
Input = b7, b6
1, X
format (a)
1, X format (c)
ROW
0, 0
format (b) 0, 0
0, 1
X, X
DAc
FIGURE 3. Transmission State Diagram
3.2 Address bus administrator
The administrator manages bus address arbitration of internal registers or user fonts RAM during external data write in. The external data write through serial data interface to registers must be synchronized by internal display timing. In addition, the administrator also provides automatic increment to address bus when external write using format (c).
3.3 Vertical display control
The vertical display control can generates different vertical display sizes for most display standards in current monitors. The vertical display size is calculated with the information of double character height bit(CHS), vertical display height control register(CH6-CH0).The algorithm of repeating character line display are shown as Table 2 and Table 3. The programmable vertical size range is 270 lines to maximum 2130 lines.
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X, X
COLc
X X,
1 0,
COLab
1, X
DAab
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MTV121
The vertical display center for full screen display could be figured out according to the information of vertical starting position register (VERTD) and VFLB input. The vertical delay starting from the leading edge of VFLB, is calculated with the following equation: Vertical delay time = ( VERTD * 4 + 1 ) * H TABLE 2. Repeat line weight of character CH6 - CH0 CH6,CH5=11 CH6,CH5=10 CH6,CH5=0x CH4=1 CH3=1 CH2=1 CH1=1 CH0=1 Repeat Line Weight +18*3 +18*2 +18 +16 +8 +4 +2 +1 Where H = one horizontal line display time
TABLE 3. Repeat line number of character Repeat Line # Repeat Line Weight 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 +1 v +2 v v +4 v v v v +8 v v v v v v v v +16 v v v v v v v v v v v v v v v v +17 v v v v v v v v v v v v v v v v v +18 v v v v v v v v v v v v v v v v v v Note:" v " means the nth line in the character would be repeated once, while " - " means the nth line in the character would not be repeated.
3.4 Horizontal display control
The horizontal display control is used to generate control timing for horizontal display based on double character width bit (CWS), horizontal positioning register (HORD), horizontal resolution register (HORR), and HFLB input. A horizontal display line consists of (HORR*12) dots which include 360 dots for 30 display characters and the remaining dots for blank region. The horizontal delay starting from HFLB leading edge is calculated with the following equation, Horizontal delay time = ( HORD * 6 + 49) * P Where P = 1 XIN pixel display time
3.5 Display & Row control registers
The internal RAM contains display and row control registers. The display registers have 450 locations which are allocated between (row 0, column 0) to (row 14, column 29), as shown in Figure 4. Each display register has its corresponding character address on ADDRESS byte, its corresponding background color, 1 blink bit and its corresponding color bits on ATTRIBUTE bytes. The row control register is allocated at column 30 for row 0 to row 14, it is used to set character size to each respective row. If double width character is chosen, only even column characters could be displayed on screen and the odd column characters will be hidden.
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ROW # 01 0 1 COLUMN # 28 29 30
MTV121
31 R E S E R V E D
DISPLAY REGISTERS
ROW CTRL REG
13 14 COLUMN# 6 89 11 WINDOW3 WINDOW4 FIGURE 4. Memory Map ADDRESS BYTE b7 b6 MSB CRADDR - Define ROM character address. ATTRIBUTE BYTE b7 b6 BGR
ROW 15
0 2 WINDOW1
3 5 WINDOW2
12 22 FRAME CRTL REG
23 30 PWM D/A CRTL REG
b5
b4 b3 CRADDR
b2
b1
b0 LSB
b5 BGG
b4 BGB
b3 BLINK
b2 R
b1 G
b0 B
BGR, BGG, BGB - These three bits define the color of the background for its relative address character. If all three bits are clear, no background will be shown(transparent). Therefore, total 7 background color can be selected. BLINK - Enable blinking effect while this bit is set to " 1 ". And the blinking is alternate per 32 vertical frames. R, G, B - These three bits are used to specify its relative address character color. 1. Row Control Registers, (Row 0 - 14) b7 b6 b5 b4 b3 b2 b1 CHS b0 CWS
COLN 30
CHS - Define double height character to the respective row. CWS - Define double width character to the respective row.
3.6 Character ROM
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MTV121
MTV121 character ROM contains 272 built-in characters and symbols including 256 standard fonts and 16 multi-color fonts. The 256 standard fonts are located from address 0 to 255. And the 16 multi-color fonts are located from address 240 to 255 while CFONT bit is set to "1". Each character and symbol consists of 12x18 dots matrix. The detail pattern structures for each character and symbols are shown in "CHARACTERS AND SYMBOLS PATTERN" on page 18.
3.7 Multi-Color Font
The color fonts comprises three different R, G, B fonts. When the code of color font is accessed, the separate R/G/B dot pattern is output to corresponding R/G/B output. See Figure 5 for the sample displayed color font. Note: No black color can defined in color font, black window underline the color font can make the dots become black in color. The detail pattern structures for each character and symbols are shown in "CHARACTERS AND SYMBOLS PATTERN" on page 18. B G R Magent Green Blue Cyan
FIGURE 5. Example of Multi-Color Font TABLE 4. The Multi-Color Font Color Selection Background Color Blue Green Cyan Red Magent Yellow White R 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1
3.8 Luminance & border generator
There are 2 shift registers included in the design which can shift out of luminance and border dots to color encoder. The bordering and shadowing feature is configured in this block. For bordering effect, the character will be enveloped with blackedge on four sides. For shadowing effect, the character is enveloped with blackedge for right and bottom sides only.
3.9 Window and frame control
The display frame position is completely controlled by the contents of VERTD and HORD. The window size and position control are specified in column 0 to 11 on row 15 of memory map, as shown in Figure 4. Window
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1. Window control registers, ROW 15 b7 b6 b5 Column ROW START ADDR 0,3,6,OR 9 MSB b7 Column 1,4,7,OR 10 MSB b7 MSB b6 b5 b4 COL END ADDR
MTV121
1 has the highest priority, and window 4 is the least, when two windows are overlapping. More detailed information is described as follows:
b4
b3
b2 b1 ROW END ADDR
b0 LSB
LSB MSB b3 LSB b3 LSB b2 WEN b2 R b1 b1 G
b6 b5 b4 COL START ADDR
b0 WSHD b0 B
Column 2,5,8,OR 11
START(END) ADDR - These addresses are used to specify the window size. It should be noted that when the start address is greater than the end address, the window will be disabled. WEN - Enable the window display. WSHD - Enable shadowing on the window. R, G, B - Specify the color of the relative background window. 2. Frame control registers, ROW 15 b7 b6 Column 12 MSBLSB VERTD - Specify the starting position for vertical display. The total steps are 256, and the increment of each step is 4 Horizontal display lines. The initial value is 4 after power up. b7 Column 13 MSBLSB HORD - Define the starting position for horizontal display. The total steps are 256, and the increment of each step is 6 dots. The initial value is 15 after power up. Column 14 b7 b6 CH6 b5 CH5 b4 CH4 b3 CH3 b2 CH2 b1 CH1 b0 CH0 b6 b5 b4 b3 HORD b2 b1 b0
b5
b4 b3 VERTD
b2
b1
b0
CH6-CH0 - Define the character vertical height, the height is programmable from 18 to 71 lines. The character vertical height is at least 18 lines if the contents of CH6-CH0 is less than 18. For example, when the contents is " 2 ", the character vertical height is regarded as equal to 20 lines. And if the contents of CH4-CH0 is greater than or equal to 18, it will be regarded as equal to 17. See Table 2 and Table 3 for detail description of this operation.
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Column 15 b7 b6 b5 b4 b3 Reserved b2 b1 b0
MTV121
This byte is reserved for internal testing. b7 b6 b5 b4 MSBLSB RSPACE - Define the row to row spacing in unit of horizontal line. That is, extra RSPACE horizontal lines will be appended below each display row, and the maximum space is 31 lines. The initial value is 0 after power up. Column 17 b7 OSDEN b6 BSEN b5 SHADOW b4 FAN b3 BLANK b2 WENCLR b1 RAMCLR b0 FBKGC b3 b2 b1 RSPACE b0
Column 16
OSDEN - Activate the OSD operation when this bit is set to "1". The initial value is 0 after power up. BSEN - Enable the bordering and shadowing effect. SHADOW - Activate the shadowing effect if this bit is set, otherwise the bordering is chosen. FAN - Enable the fade-in/fade-out function when OSD is turned on from off state or vice verca. The function roughly takes about one second to fully display the whole menu or to disappear completely. BLANK - Force the FBKG pin output to high while this bit is set to "1". WENCLR - Clear all WEN bits of window control registers when this bit is set to "1". The initial value is 0 after power up. RAMCLR - Clear all ADDRESS bytes, BGR, BGG, BGB and BLINK bits of display registers when this bit is set to "1". The initial value is 0 after power up. FBKGC - Define the output configuration for FBKG pin. When it is set to "0", the FBKG outputs during the displaying of characters or windows, otherwise, it outputs only during the displaying of character. Column 18 B7 TRIC b6 FBKGP b5 PWMCK b4 DWE b3 HSP b2 VSP b1 PWM1 b0 PWM0
TRIC - Define the driving state of output pins ROUT, GOUT, BOUT and FBKG when OSD is disabled. That is, while OSD is disabled, these four pins will drive low if this bit is set to 1, otherwise these four pins are in high impedance state. The initial value is 0 after power up. FBKGP - Select the polarity of the output pin FBKG =1 Positive polarity FBKG output is selected. =0 Negative polarity FBKG output is selected. The initial value is 1 after power up. PWMCK - Select the output options to HTONE/PWMCK pin. =0 HTONE option is selected. =1 PWMCK option is selected with 50/50 duty cycle and synchronous with the input HFLB. The frequency is selected by (PWM1, PWM0) shown as Table 5.
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The initial value is 0 after power up.
MTV121
DWE - Enable double width. When the bit is set to "1", the display of OSD menu can change to half resolution for double character width, and then the number of pixels of each line should be even. The initial value is 0 after power up. HSP = 1 Accept positive polarity Hsync input. = 0 Accept negative polarity Hsync input. = 1 Accept positive polarity Vsync input. = 0 Accept negative polarity Vsync input.
VSP -
PWM1, PWM0 - Select the PWMCK output frequency. = (0, 0) XIN frequency /8 = (0, 1) XIN frequency /4 = (1, 0) XIN frequency /2 = (1, 1) XIN frequency /1 The initial value is (0, 0) after power up. Notes : When XIN is not present, don' write data in any address. If data is written in any other address, a t malfunction may occur. TABLE 5. PWMCK Frequency and PWMDA sampling rate (PWM1, PWM0) ( 0, 0 ) ( 0, 1 ) ( 1, 0 ) ( 1 ,1 ) B7 PWMCK Freq XIN frequency /8 XIN frequency /4 XIN frequency /2 XIN frequency /1 b6 WSR b5 WSG b4 WSB b3 PWMDA sampling rate XIN frequency /(8 * 256) XIN frequency /(4 * 256) XIN frequency /(2 * 256) XIN frequency /(1 * 256) b2 CSR b1 CSG b0 CSB
Column 19
WSR, WSG, WSB - Define the color of shadowing on windows. The initial value is (0, 0, 0) after power up. CSR, CSG, CSB - Define the color of bordering or shadowing on characters. The initial value is (0, 0, 0) after power up. B7 b6 b5 b4 b3 b2 b1 b0 CFONT
Column 20
CFONT - Enable 16 multi-color fonts. = 0 Character address 240 to 255 are connected to standard ROM fonts. = 1 Character address 240 to 255 are connected to 16 multi-color ROM fonts. The initial value is 0 after power up.
Column 21
B7 WW41
b6 WW40
b5 WW31
b4 WW30
b3 WW21
b2 WW20
b1 WW11
b0 WW10
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TABLE 6. Shadow Width Setting (WW41, WW40) Shadow Width (unit in Pixel) (0, 0) 2 (0, 1) 4 (1, 0) 6 (1, 1) 8
MTV121
WW41, WW40 - Determines the shadow width of the window 4 when WSHD bit of th window 4 is enabled. Please refer to the Table 6 for more details.
WW31, WW30 - Determines the shadow width of the window 3 when WSHD bit of th window 3 is enabled. WW21, WW20 - Determines the shadow width of the window 2 when WSHD bit of th window 2 is enabled. WW11, WW10 - Determines the shadow width of the window 1 when WSHD bit of th window 1 is enabled. B7 WH41 b6 WH40 b5 WH31 b4 WH30 b3 WH21 b2 WH20 b1 WH11 b0 WH10
Column 22
WH41, WH40 - Determines the shadow height of the window 4 when WSHD bit of th window 4 is enabled. Please refer to the Table 7 for more details. TABLE 7. Shadow Height Setting (WH41, WH40) Shadow Height (unit in Line) (0, 0) 2 (0, 1) 4 (1, 0) 6 (1, 1) 8
WH31, WH30 - Determines the shadow height of the window 3 when WSHD bit of th window 3 is enabled. WH21, WH20 - Determines the shadow height of the window 2 when WSHD bit of th window 2 is enabled. WH11, WH10 - Determines the shadow height of the window 1 when WSHD bit of th window 1 is enabled.
3.10 Color encoder
The decoder generates the video output to ROUT, GOUT and BOUT by integrating window color, border blackedge, luminance output and color selection output (R, G, B) to form the desired video outputs.
M Pixels N Horizontal lines
WINDOW AREA
Note: M and N are defined by the registers of row 15, column 21 and 22.
N Horizontal lines
Bordering
Shadowing
M Pixels
FIGURE 6. Character Bordering and Shadowing and Shadowing on Window
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3.11 PWM D/A converter
MTV121
There are 8 open-drain PWM D/A outputs (PWM0 to PWM7). These PWM D/A converter outputs pulse width are programmable by writing data to Column 19 to 26 registers of Row 15 with 8-bit resolution to control the pulse width duration from 0/256 to 255/256. And the sampling rate is selected by (PWM1, PWM0) shown as table 5. In applications, all open-drain output pins should be pulled-up by external resistors to supply voltage (5V to 9V) for desired output range. b7 Column 23 | Column 30 MSB b6 b5 b4 b3 PWMDA0 | PWMDA7 b2 b1 b0
LSB
PWMDA0 - PWMDA7 - Define the output pulse width of pin PWM0 to PWM7.
PWMCK 255 PWM0 PWM1 PWM2 0 1 2 3
m
m+1
255
0
1
2
3
PWM6 PWM7
FIGURE 7. 8 Channel PWM Output Rising Edges Are Separated by Half PWMCK B7 0 b6 0 b5 0 b4 0 b3 0 b2 0 b1 0 b0 0
Column 31
Note: The byte is reserved for the testing. Write " Ax " will enter into test mode and write " 00 " in normal operation.
4.0 ABSOLUTE MAXIMUM RATINGS
DC Supply Voltage(VDD) Voltage with respect to Ground Storage Temperature Ambient Operating Temperature -0.3 to +7 V -0.3 to VDD+0.3 V -65 to +150 oC 0 to +70 oC
5.0 OPERATING CONDITIONS
DC Supply Voltage(VDD) Operating Temperature +4.75 to +5.25 V 0 to +70 oC
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6.0 ELECTRICAL CHARACTERISTICS (Under Operating Conditions)
Symbol VIH VIL VOH VOL VODH Parameter Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Open Drain Output High Voltage Open Drain Output Low Voltage Operating Current Standby Current Conditions (Notes) IOH -5 mA IOL 5 mA (For all OD pins, and pulled up by external 5 to 9V power supply) 5 mA IDOL ( For all OD pins ) Pixel rate=96MHz Iload = 0uA Vin = VDD, Iload = 0uA Min. 0.7 * VDD VSS-0.3 VDD-0.8 -
MTV121
Max. VDD+0.3 0.3 * VDD (0.2 * VDD for SSB pin) 0.5
Units V V V V
5
9
V
VODL ICC ISB
-
0.5 25 12
V mA mA
7.0 SWITCHING CHARACTERISTIC (Under Operating Conditions)
Symbol fHFLB Tr Tf tBCSU tBCH tDCSU tDCH tSCKH tSCKL tSU:STA tHD:STA tSU:STO tHD:STO tSETUP tHOLD tpd PIXin Parameter HFLB input frequency Output rise time Output fall time SSB to SCK set up time SSB to SCK hold time SDA to SCK set up time SDA to SCK hold time SCK high time SCK low time START condition setup time START condition hold time STOP condition setup time STOP condition hold time HFLB delay to rising edge of pixel clock minimum pulse width of HFLB propagation delay of output to pixel clock pixel clock input 6 Min. 15 200 100 200 100 500 500 500 500 500 500 2 25 10 96 Typ. Max. 130 5 5 6 Units KHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz
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MTV121 Revision 5.0 06/29/1999
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8.0 TIMING DIAGRAMS
tSCKH
MTV121
SCK
tSCKL
SSB
tBCSU tBCH
SDA
tDCSU tDCH
FIGURE 8. Data interface timing(SPI)
tSCKH
SCK
tSU:STA tSCKL tHD:STO
SDA
tHD:STA tDCSU tDCH tSU:STO
FIGURE 9. Data interface timing(I2C)
PlXin R,G,B, FBKG HTONE tpd tpd:: Propagation Delay to R,G,B, FBKG
and HTONE outputs
HFLB
t SETUP t HOLD
FIGURE 10. Output and HFLB Timing to Pixel Clock
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MTV121 Revision 5.0 06/29/1999
MYSON TECHNOLOGY
9.0 PACKAGE DEMENSION
9.1 16 Pin PDIP 300mil
MTV121
312 +/-12 55 +/-20 R40 250 +/-4
R10Max (4X ) 90 +/-20 350 +/-20
75 +/-20 90 +/-20 750 +/-10 15 Max 7 Typ
65 +/-4 55 +/-4 310Max
10
35 +/-5
115 Min 100Ty p 18 +/2Typ 60 +/5Typ 15 Min
9.2 20 Pin PDIP 300mil
312 +/-12 55 +/-20 R40 250 +/-4
R10Max (4X ) 90 +/-20 350 +/-20
75 +/-20 90 +/-20 1020 +/-10 15 Max 7 Typ
65 +/-4 55 +/-4 310Max
10
35 +/-5 115 Min 15 Min 100Typ 18 +/-2Typ 60 +/-5Typ
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MTV121 Revision 5.0 06/29/1999
MYSON TECHNOLOGY
9.3 24 Pin PDIP 300mil
R10Max (4X)
MTV121
312+/-12
80+/-20
350+/-20 250+/-4
R40
55+/-20
930+/-10 1245+/-10 15Max 7Ty p 35+/-5
10 65+/-4 65+/-4
115Min
15Min. 100Ty p 18+/2Typ 60+/5Typ
9.4 16 Pin SOP 300mil
0.406 +/-0.013 0.295 +/-0.004
0.406 +/-0.008 (4x)
0.015x45o
7o(4x)
0.091
0.098 +/-0.006
0.016 +/-0.004
0.050
0.028 +0.022 /-0.013
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MTV121 Revision 5.0 06/29/1999
MYSON TECHNOLOGY
9.5 20 Pin SOP 300 mil
MTV121
0.502+/-0.006inch 20 11 0.406+/-0.012inch
0.295+/-0.004inch 0.020x45
1 0.016typ.
10 0.050typ.
9.6 24 Pin SOP 300mil
15.0mm /+0.4 -0.1 24 13 1.85mm/+0.4 -0.15
7.9mm+/0.4 5.3mm +0.3/0.1
6.9m m
0.1mm +0.2/-0.05
0.5mm+/-0.2
1 0.45mm +/0.1 1.27m m
12
0.2mm +0.1/-0.05
10.0 CHARACTERS AND SYMBOLS PATTERN
Please see the attachment.
Myson Technology, Inc. http://www.myson.com.tw No. 2, Industry E. Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C. Tel: 886-3-5784866 Fax: 886-3-5785002
Myson Technology USA, Inc. http://www.myson.com 20111 Stevens Creek Blvd. #138 Cupertino, Ca. 95014, U.S.A. Tel:408-252-8788 FAX: 408-252-8789 Sales@myson.com
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MTV121 Revision 5.0 06/29/1999

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